With electronic devices, particularly portable devices such as mobile phones, becoming smaller and yet at the same time offering a wider range of functions, there is a need to integrate multifunctional chips without increasing the size of the devices and keeping a small form factor. Increasing the number of electronic components in a 2D structure is incompatible with these objectives, and therefore 3D packages are increasingly being adopted in order to provide greater functionality and higher component density with a small form factor.
In a 3D structure, electronic components such as semiconductor chips may be provided in a multilayer stacked structure. In this case, wafers or die may be “stacked” on one another. While 3D integration increases circuit density, it has various drawbacks, such as increased cost due to the use of additional wafers, increased testing time and cost, and increased assembly time and cost. It is therefore desirable to have improvements to increase circuit density.